1. Field of the Invention
The present invention relates to a technique for reducing the time required to determine the most significant digit of the result produced by combining two or more operands together.
2. Description of the Prior Art
In the addition of floating point numbers, each number to be added (addend) is represented by a mantissa and an exponent. To perform the addition, the mantissa of one of the addends is shifted until the exponents match. Normally, the addend having the larger exponent remains unshifted, whereas the addend having the smaller exponent has its mantissa shifted a given number of places to the right (that is, towards the least significant digit), while increasing its exponent a comparable amount until it equals the exponent of the larger addend. Then, the two mantissas are added to obtain a sum. If more than two addends are to be added, all but the largest addend can be thus adjusted prior to the addition. If the mantissas that are added together are of the same sign, then the sum may be so large that it has to be shifted to the right to normalize it. If the mantissas are of opposite sign, then cancellation may occur such that the sum needs to be shifted to the left to normalize it. Normalization is achieved when the most significant digit of the sum occupies the most significant digit position of the result.
In many types of adder circuits, for example, integrated circuits employing microprocessing circuitry, it is desired that the most significant digit of the sum occupy the most significant digit position in a register or other circuit embodiment. To obtain this result in the prior art, a shifter is typically employed to shift the sum output of the adder circuitry to the left or right, until the most significant digit occupies the most significant digit position. The exponent of the sum is adjusted accordingly, being increased one digit for each position that the sum is shifted towards the left, or decreased one digit for each position that the sum is shifted to the right. Thus, the prior art technique requires that the sum be available before the normalization is initiated.
It is desirable to speed up the time required to obtain the sum from an adder circuit and normalize it as described. In particular, most computational circuitry is clocked to operate on machine cycles, wherein one or more operations are performed during a given cycle. It is desirable to maximize the amount of useful computation that can be obtained in each machine cycle, and thereby reduce the total time required to achieve a given result. For this purpose, "parallelism" is often utilized for performing more than one type of operation simultaneously. Usually, operations that are considered for parallel implementation are those that are independent; that is, the result of one does not depend upon the result of another.